Evaluation system for the Mira130 CMOS image sensor with NIR-enhanced performance
General Description
The JetCis evaluation system is available for the evaluation of the Mira130 1.3MP global shutter NIR image sensor which provides enhanced QE in the near-infrared range and allows superior power consumption reduction of 3D systems. The system permits raw image capture for a complete sensor evaluation and supports 1 or 2 MIPI CSI-2 lanes. The JetCis features an open development platform based on Linux running on a nVidia Jetson Nano embedded system. Also included is a graphical user interface offering a wide range of sensor controls such as black level correction, exposure control, HDR as well as analysis options such as histograms and line profiles.
Technical Documents
| Type | Description | Language | ||
|---|---|---|---|---|
| Quick Start Guide | JetCis Evaluation Platform | English |
Resources
| Type | Description | Language | ||
|---|---|---|---|---|
| Evaluation Software | Mira_EvalSW_jetcis_v3-1-1.zip eval kit software for mira sensor on jetson nano | EN | ||
| Evaluation Software | Mira_EvalSW_jetcis_v3-0-2.zip | EN | ||
| Evaluation Software | Mira_EvalSW_jetcis_v3-0-1.zip software for nvidia based evaluation kit (jetcis) | EN |
Related Products
Mira130
Mira130
Mira130 is a global shutter CMOS image sensor with NIR enhancement of the QE. Target QE is 40% at 940nm, and 58% at 850nm.
It outputs monochrome images with an effective pixel array of 1080H × 1280V, and supports complex on-chip operations such as high dynamic range (HDR) mode, external triggering, windowing, horizontal or vertical mirroring. Its maximum frame rate is 120fps at a full image resolution. On-chip registers can be accessed via the standard I2C interface.
It outputs monochrome images with an effective pixel array of 1080H × 1280V, and supports complex on-chip operations such as high dynamic range (HDR) mode, external triggering, windowing, horizontal or vertical mirroring. Its maximum frame rate is 120fps at a full image resolution. On-chip registers can be accessed via the standard I2C interface.