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Staff Engineer, Analog/Mixed Signal Verification and Design

工作编号

003547

职位类型

Research & Development

工作时间

  • Regular Fulltime

工作地点

Rapperswil

待遇:

描述列表

  • Responsible for planning & executing mixed-signal top-level IC verification for audio sensors
  • Develop test benches with high degree of automation
  • Implement mixed-signal behavioral models
  • Generate documentation for design verification planning & execution as well as customer reviews
  • Collaborate with digital verification engineers to achieve overall verification coverage
  • Support IC validation and production test (ATE) development
  • Ensure adoption of DV best practices, procedures and improvements within organization
  • Contribute to internal and external design & verification reviews

教育列表

  • Degree in Electronic Engineering or related field
  • Knowledge in digital and mixed-signal design and verification
  • Experience with Cadence AMS Designer and modelling in VerilogAMS
  • Experience with Universal Verification Method (UVM) and modelling in SystemVerilog is an advantage
  • Natural interest in EDA tools, persistent in solving software tool issues
  • Experience in verification coverage tracking
  • Programming skills in Linux shell, C, Perl and Tcl is an advantage
  • Structured and methodological approach
  • Strong team player
  • Excellent spoken and written communication skills in English

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