Open Position Banner

자산 발행인

angle-left jobno-003547-Switzerland

Analog/Mixed Signal Verification and Design Engineer

직무 번호

003547

직종

Research & Development

근무 시간

  • Regular Fulltime

채용 지역

Rapperswil

우리가 제공하는 것:

설명 목록

  • Responsible for planning & executing mixed-signal top-level IC verification for audio sensors
  • Develop test benches with high degree of automation
  • Implement mixed-signal behavioral models
  • Generate documentation for design verification planning & execution as well as customer reviews
  • Collaborate with digital verification engineers to achieve overall verification coverage
  • Support IC validation and production test (ATE) development
  • Ensure adoption of DV best practices, procedures and improvements within organization
  • Contribute to internal and external design & verification reviews

교육 목록

  • Degree in Electronic Engineering or related field
  • Knowledge in digital and mixed-signal design and verification
  • Experience with Cadence AMS Designer and modelling in VerilogAMS
  • Experience with Universal Verification Method (UVM) and modelling in SystemVerilog is an advantage
  • Natural interest in EDA tools, persistent in solving software tool issues
  • Experience in verification coverage tracking
  • Programming skills in Linux shell, C, Perl and Tcl is an advantage
  • Structured and methodological approach
  • Strong team player
  • Excellent spoken and written communication skills in English

Set up Job Alert

Job Alert

 

You haven't found what you were looking for? Stay up to date and set up your personal ams job alert. Subscribe to your personal job alert now! 

HR Contact

Contact

 

Contact our Talent Managers