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Senior Staff Engineer, Physical Design
Research & Development
- Regular Fulltime
- Block/Chip physical design floor-planning, power-planning, implementation and integration in CMOS process
- Design functional equivalence, timing/performance, signal integrity checks and IR analysis.
- Physical Verification for DRC/LVS, reliability and power checks
- Leading and mentoring junior employees and contractors in the team
- Technical communication with customer (and/or marketing) and other work-packages, including: presentation in design reviews, test requirements, defining / tracking / working to ensure schedule adherence, interactive problem solving and customer communication under pressure.
- Experience with EM/IR: Voltus or Apache RedHawk is preferred
- Create and patent new IPs
- High level of proficiency in design flow, synchronization, STA, design-for-test (DfT), place and route (PnR), ATPG
- Internal team leadership and communication, coordination of design requirements and tradeoffs, preparation for weekly meetings (internal and customer)
- Interact with FE team to understand timing and CTS requirements and achieve best quality results
- M.Tech/B.Tech in VLSI/Electronics/Electrical domain or any equivalent post graduation training from recognized institute.
- Hands on experience in PD flow from Netlist to GDSII in CMOS process technologies 55nm or below
- Strong knowledge in CTS implementation methodologies
- Experience in Physical Verification and closure in 55nm or below technology nodes.
- Knowledge of MCMM optimization and multi power domain designs
- Experience in Static Timing Analysis with Signal Integrity.
- Experience in Synthesis, LEC, DFT is plus.
- Tools : Innovus/ICC2, Calibre, Primetime-SI, Tempus, QRC/StarRC, LEC, Voltus
- Experience with relevant CAD tools (used for digital IC Physical design and LVS &DRC verification)
- Affinity with sensors and lasers
- Excellent presentation and communication skills
- Initiative, enthusiasm, systematic and analytic approach
- Team player/driver
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