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Development of flow to auto-generate the framework of analog models for digital and mixed-signal verification. - Munich, Germany

Development of flow to auto-generate the framework of analog models for digital and mixed-signal verification.

Job no.

007066

Position Type

Research & Development

Working time

  • Master/Bachelor (student) Thesis

Place of employment

Munich

What we offer:

Your tasks and responsibilities

  • Learn analog behavioral modelling techniques and simulation environment
  • Conduct feasibilities to create a generic framework for analog real-number (RNM) behavioral models using System Verilog
  • Develop a Python-based automated flow to translate feasibility studies
  • Perform model validation (schematic versus model simulation) using proposed flow
  • Document the flow and conduct internal review meetings

Your education and experiences

  • Basic knowledge in digital and/or analog circuit design
  • Knowledge in scripting languages (preferable Python)
  • Bachelor’s degree in electrical engineering or some related field
  • Interest to deepen knowledge and skills in analog mixed-signal IC verification
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