Job no.

007039

Position Type

Research & Development

Working time

• Regular Fulltime

Place of employment

Plano, TX

What we offer:

Your tasks and responsibilities

• Responsible for design verification and validation of integrated circuits, using both directed tests and constrained random regressions
• Creation and validation of System Verilog models for mixed signal circuit blocks
• Proficiency in System Verilog including: writing checkers and assertions, customizing constraints, getting functional coverage collection using cover groups, etc.
• Experience running analog (SPICE) and digital simulators are a strong advantages.
• Creation of test benches and automated verification simulations
• Performing block level and top level design verification
• Generation of relevant documentation (DV Plan, DV execution plan, customer reviews, etc.)

Your education and experiences

• Working towards a Bachelors' or Masters' degree in Computer Engineering, Electrical Engineering or relevant degree.
• Course work related to design verification, block level model specifications, simulation, system verilog real number modeling, etc.
• System Verilog / UVM based DV experience
• Experience with relevant CAD tools (including Cadence Virtuoso, SPICE, etc.)
• Ability to read analog schematics and extract related main functionality.
• Experience modeling mixed signal/RF blocks including biasing networks, power regulators, bandgaps, Opamp’s, OTA’s, data converters, LNA, PA, mixers, couplers, splitters, combiners, etc…
• Strong verbal and written communication skills