Junior Analog Layout Engineer (part-time) (m/f/d)
Research & Development
- Regular Parttime
Place of employment
What we offer:
Your tasks and responsibilities
- Responsible for designing physical layout of full custom analog cells or blocks
- Fulfill all necessary rules and production relevant topics
- Responsible for debugging LVS & DRC errors
- Experience with CAD systems helpful
Your education and experiences
- Familiarity with basics of analog and mixed signal structures
- Soft Skills: Good communication, problem solving skills and team player
- Good English language skills are required
Collective salary and wage agreement
We offer competitive salaries and additional benefits
based on your performance, experience and qualification.
The employment is in accordance with the collective salary and wage agreement for employees of the electrical and electronics industry, employment group E (http://www.feei.at/kollektivvertraege/kv_tabelle/).
We offer a higher compensation depending on your expertise and skills.