Job no.

006920

Position Type

Research & Development

Working time

• Regular Fulltime

Place of employment

Hyderabad

What we offer:

Your tasks and responsibilities

• Staff Design Enablement Engineer
• Digital Design Front-End support for EDA design tools and methodology
• DFT flow - tool support, design implementation, optimization and debug.
• RTL HDL verification (Verilog, SV) – lint, CDC, RDC
• Be ready to actively participate in specific design tasks of ongoing projects

Your education and experiences

• 5+ years’ experience in Digital IC Design ASIC implementation, with proficiency in digital frontend design.
• Deep knowledge of RTL2GDS flow, HDL design and verification, synthesis, scan insertion and ATPG
• Knowledge of Cadence tools (Genus, Modus, LEC, Conformal) and DFT (Compression, LBIST, ATPG, pattern generation and debug) are a strong plus
• Excellent presentation skills, initiative, enthusiasm