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Senior Staff Engineer Layout (m/f/d) - Premstätten, Austria

Senior Staff Engineer Layout (m/f/d)

Job no.


Position Type

Research & Development

Working time

  • Regular Fulltime

Place of employment


What we offer:

Your tasks and responsibilities

  • Analog layout and extracted view generation for RnD related structures as well as for cluster layouts (MPW)
  • Physical verification such as DRC / LVS / Antenna / DFM etc. using Mentor & Cadence tools
  • Fab data submission support via tapeout office
  • Close technical contact with various foundries
  • Project management/coordination (in the role of a top level layout lead)
  • Interaction with Device Physicists / EDA Engineers / Quality Engineers / IP Development Engineers
  • Working in the fields of layout automation (SKILL language, Python, etc…)
  • Driving new ideas about fast layout implementation for leading edge technologies
  • Supervision/mentoring of young/external colleagues

Your education and experiences

  • Technical Degree or higher is a must
  • Min. 5 years proven track record in semiconductor industry (layout / physical design)
  • High degree of expertise on Cadence Virtuoso tools
  • Strong knowledge about CMOS Semiconductors (including deep submicron technologies)
  • Very good understanding about physical verification of layouts
  • Coding experience (such as SKILL language) beneficial but not a must
  • Good understanding of analog circuit design is beneficial
  • Good communication in English is a must
  • Good team player / working with international teams
  • Proactively driving new ideas inside RnD department and beyond
  • Good reporting skills

Collective salary and wage agreement

We offer competitive salaries and additional benefits based on your performance, experience and qualification.
The employment is in accordance with the collective salary and wage agreement for employees of the electrical and electronics industry, employment group H (
We offer a higher compensation depending on your expertise and skills.

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