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Senior Staff Design Verification Engineer (m/f/d) - Premstätten, Austria

Senior Staff Design Verification Engineer (m/f/d)

Job no.

006584

Position Type

Research & Development

Working time

  • Regular Fulltime

Place of employment

Premstätten

What we offer:

Your tasks and responsibilities

  • Definition and implemention of ASIC design verification environment for Time of Flight sensors
  • Proactive work with RTL Design, Verification and chip architecture teams to ensure that the chip meets all the featured requirements. Make decision of right verification methodology based on type of design
  • Plan, architect and develop SystemVerilog /UVM test bench, including writing checkers and assertions, customizing constraints, getting functional coverage collection using cover groups, etc. Develop test bench for ARM CPU based AMBA architecture design.
  • Understand automated model vs schematic simulation
  • Develop support utilities for verification automation, test bench automation, regression and other verification enhancements to improve productivity and functional coverage
  • Development of verification test plans, test suites and verification activities which includes environment bring-up, regressions, failure debug, and netlist simulation for tape-out, develop detailed test and coverage plans based on IC specifications
  • Review the work done by juniors or external verification team on every project base.
  • Supporting mixed signal verification which includes analog and Verilog RTL in same simulation environment
  • Performing block level and top level design verification
  • Technical communication with customer (and/or marketing) and other work-packages, including: presentation in design reviews, test requirements, defining / tracking / working to ensure schedule adherence, interactive problem solving and customer communication under pressure
  • Generation of relevant documentation (DV Plan, DV execution plan, customer reviews, etc.)
  • Create and patent new IPs

Your education and experiences

  • University degree in Electrical Engineering or similar
  • Minimum 4 years’ experience in ASIC verification environment, with expertise in systemverilog, UVM, verification methodologies
  • Expertise in design verification methodologies such as UVM, assertion based coverage driven verification (code & functional coverage), constraint random test generation
  • Experience with mixed mode and analog simulation environments
  • Experience in defining verification environment, Test bench architecture.
  • Experience with CPU based design (ARM) and AMBA bus architecture.
  • Experience in generating verification plan from specification. Creating verification matrix, defining functional bins, writing functional cover point and meeting functional coverage goals and bug management schemes, with strong debugging skills. (irun, xcelium, Cadense IMC, vManager).
  • Experience in Formal Verification is plus. (OneSpin etc)
  • Strong knowledge of serial protocol like I2C, I3C, SPI etc. and its verification.
  • Experienced on Make and proficient in scripting using perl, shell, Tcl, etc. to automate the verification process
  • Self-motivated and should be able to work independently
  • Should have worked in verifying mixed signal blocks in digital perspective.
  • Strong knowledge of analog blocks like different ADC, DAC, Integrator, POR, Amplifiers and power management block.
  • Excellent team player should be able to understand team dynamic
  • Strong written and verbal communication skills, fluent in English
  • Initiative, enthusiasm, systematic and analytic approach
  • Team player/driver

Collective salary and wage agreement

We offer competitive salaries and additional benefits based on your performance, experience and qualification.
The employment is in accordance with the collective salary and wage agreement for employees of the electrical and electronics industry, employment group H (http://www.feei.at/kollektivvertraege/kv_tabelle/).
We offer a higher compensation depending on your expertise and skills.

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