Senior Staff Digital Design Engineer (m/f/d)
Research & Development
- Regular Fulltime
Place of employment
What we offer:
Your tasks and responsibilities
- Define digital/system architecture as per system requirement.
- Understand/derive spec, design partitioning and implement blocks in SV RTL accordingly.
- Interact with Analog engineers; derive/define specification.
- Verify the design implementation at block level using block level test bench or existing top-level test bench.
- Define/Architect CPU based design, interact with SW team and define functions such that SW/HW interface is clean. Define and implement debugging, memory map and Bootup logic etc.
- Synthesis, scan insertion and ATPG generation. Define/Write assertion in the design. CDC, RDC, logic check by Questa/spyglass, LINT. Handle projects design independently. Review the work done by juniors or design team on every project base.
- Provide training to juniors, learn new concepts and contribute to growth of team. Handle internships. Create and patent new IPs.
- Post Silicon debug and check functionality in lab
- Technical communication with customer (and/or marketing) and other work-packages, including: presentation in design reviews, test requirements, defining / tracking / working to ensure schedule adherence, interactive problem solving and customer communication under pressure
- Defining / tracking / working to ensure schedule adherence
Your education and experiences
- Master Dregree in Electrical Engineering or similar Minimum of 5 years experience in Digital IC Design ASIC development, with proficiency in design of blocks and system level design, ARM CPU based design and AMBA bus architectures.
- Expertise in Architecture development and RTL coding. Creating ARM core platform, debugging, boot logic/sequence techniques, Memory mapping etc. Must have experience in handling multiple clock domain.
- Strong knowledge of serial protocol like I2C, I3C, SPI etc. and its implementation.
- Hands on experience in verification, synthesis, scan insertion, ATPG and timing analysis, early design analysis, CDC. (irun, Xcelium, DC, Genus, Primetime, Tempus, Tetramax, spyglass, Questa). Make and proficient in scripting using perl, shell, Tcl, etc
- Experience in interacting with physical design team to complete timing closer and successful implementation.
- Experience in using UVM Testbench for verification, object oriented programming knowledge. Experience in defining assertion, writing assertions and other design methodology
- Experience/Knowledge of mixed signal blocks like ADC, DAC and other analog blocks like integrator, power management blocks from digital perspective is plus.
- Experience in DSP and implementation of different Digital Filters like CIC, decimation is plus. Experience in data representation in different numbering format and working with algorithm is plus.
- Self-motivated and ability to handle project independently. Ability to work in a dynamic & fast-paced environment, and take responsibilities pro-actively
- Optical sensor domain experience/knowledge is a plus. Experience in training the juniors and handle internships. Experience in or ability to debug Post silicon in lab and operation of lab instrument is a plus.
- Able to communicate effectively and to the point in front of customers and internal stakeholders. Excellent presentation skills.
- Initiative, enthusiasm, systematic and analytic approach; Team player/driver; Affinity with sensors and lasers; Fluency in English: written and verbal
Collective salary and wage agreement
We offer competitive salaries and additional benefits
based on your performance, experience and qualification.
The employment is in accordance with the collective salary and wage agreement for employees of the electrical and electronics industry, employment group H (http://www.feei.at/kollektivvertraege/kv_tabelle/).
We offer a higher compensation depending on your expertise and skills.