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Graduate Design Verification Engineer - Plano, TX, United States

Graduate Design Verification Engineer

Job no.

006483

Position Type

Research & Development

Working time

  • Regular Fulltime

Place of employment

Plano, TX

What we offer:

Your tasks and responsibilities

  • Responsible for design verification of mixed signal IC’s in a digital / mixed signal design environment
  • Primary focus is on mixed signal design verification, but proficiency with digital design verification (including UVM) is an plus
  • Creation and validation of System Verilog models for mixed signal circuit blocks
  • Proficiency in System Verilog including: writing checkers and assertions, customizing constraints, getting functional coverage collection using cover groups, etc.
  • Experience running both analog (SPICE) and digital simulators is a strong advantage
  • Creation of test benches and automated verification simulations
  • Performing block level and top level design verification
  • Generation of relevant documentation (DV Plan, DV execution plan, customer reviews, etc.)

Your education and experiences

  • Master’s degree in Electrical / Computer Engineering or a Bachelor’s degree with 2+ years of experience
  • System Verilog / UVM based mixed signal DV (Design Verification) experience
  • Collaborative and respectful team player with mentoring skills, and passionate about achieving team goals
  • Excellent communication skills (both oral and written) are required, as real time customer level technical interface and design / team leadership is necessary.
  • Experience with relevant CAD tools
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