Open Position Banner
Sensing is Life
Our vision is to create the uncontested leader in optical solutions through bold investments in disruptive innovation and
continuous transformation delivering best-in-class profitability and growth.
Asset Publisher

Staff Design Verification Engineer - Hyderabad, India

Staff Design Verification Engineer

Job no.

006446

Position Type

Research & Development

Working time

  • Regular Fulltime

Place of employment

Hyderabad

What we offer:

Your tasks and responsibilities

  • Implement the ASIC verification environment
  • This role requires the candidate to work with RTL Design, Verification, Architecture teams to ensure that chip meets all the feature requirements.
  • Proficiency in System Verilog and UVM, including: writing checkers and assertions, customizing constraints, getting functional coverage collection using cover groups, etc.
  • Develop support utilities for verification automation, test bench automation, regression and other verification enhancements to improve productivity and functional coverage
  • Candidate will be able to build test bench from scratch using UVM or System Verilog
  • Support the development of verification test plans, test suites and verification activities which includes environment bring-up, regressions, failure debug, and netlist simulation for tape-out, develop detailed test and coverage plans based on IC specifications

Your education and experiences

  • M.Tech/ B.Tech with 5-7 years of Digital Verification experience.
  • Experienced on design verification methodologies such as UVM, assertion based coverage driven verification (code & functional coverage), constraint random test generation
  • Experienced on developing verification environment and test cases, conducting functional simulations, writing functional cover point and meeting functional coverage goals and bug management schemes
  • Experienced on Make and proficient in scripting using Perl, shell, Tcl, etc. to automate the verification process
  • Experience in writing test plan to capture all the feature of the design under test and functional/Assertion coverage implementation
  • System Verilog, UVM, object oriented programming knowledge, Verilog
  • Added advantage if worked in verifying mixed signal blocks in digital perspective
Set up Job Alert

Job Alert

 

You haven't found what you were looking for? Stay up to date and set up your personal ams job alert. Subscribe to your personal job alert now! 

HR Contact

Contact

 

Contact our Talent Managers