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Senior Staff Design Verification Engineer
Research & Development
- Regular Fulltime
Place of employment
What we offer:
Your tasks and responsibilities
- • Lead a team of engineers to perform digital verification of circuit blocks and subsystems in Cadence and Synopsys environments using UVM methodology
- • SoC/IC verification, lab evaluation and test concept definition as core member of project team.
- • Verification planning: Define test flow and test cases to meet coverage requirements and silicon coverage.
- • Advanced modeling of system modules to make a DFM.
- • Create, debug, and run test-benches and scripts to execute transistor-level performance verification over design corners using circuit simulators
- • Proficiency in System Verilog and UVM, including: writing checkers and assertions, customizing constraints, etc.
- • Develop support utilities for verification automation, test bench automation, regression and other verification enhancements to improve productivity and functional coverage
- • Support the development of verification test plans, test suites and verification activities which includes environment bring-up, regressions, failure debug, and netlist simulation for tape-out, develop detailed test and coverage plans based on IC specifications
- • Establish cross-correlation matrices for Verification/Evaluation/ATE results.
- • Generation of relevant documentation (DV Plan, DV execution plan, customer reviews, etc.)
- • Mentoring of staff engineers for continuous improvement of the DV flow.
Your education and experiences
- . M.Tech/ B.Tech with at least 8 years of Digital Verification experience.
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