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Senior Staff Engineer, Design Verification (m/f/d) - Valencia, Spain

Senior Staff Engineer, Design Verification (m/f/d)

Job no.

006789

Position Type

Research & Development

Working time

  • Regular Fulltime

Place of employment

Valencia

What we offer:

Your tasks and responsibilities

  • Verification of integrated mixed signal and digital blocks and CMOS IC’s
  • Creation of verification plans for complex mixed signal or digital devices
  • Development of verification environment and ensure proper verification coverage for enabling bug free silicon manufacturing.
  • Creation of DV test cases and debugging of simulation results

Your education and experiences

  • University degree in Electronics or related
  • 10+year experience in digital design/verification with hands-on experience on relevant design/simulation tools
  • Knowledge of design verification methodologies, tools and languages (UVM, SystemVerilog, assertions …)
  • Analytical mind for solving complex problems and debugging design issues popping up in simulations
  • Team oriented, committed to deadlines and development discipline
  • Communication skills and proficiency in English
  • · Knowledge in other areas of Digital Design will be considered as a plus:
  • Knowledge of RTL design with HDL (Verilog/VHDL) for integrated devices. Hands-on experience with FPGA’s.
  • Knowledge of DFT and test-pattern generation
  • Knowledge of backend flow tools for design synthesis, timing sing-off and power analysis
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