Senior Staff Engineer, SW Support
Research & Development
- Regular Fulltime
Place of employment
What we offer:
Your tasks and responsibilities
- Provide leadership during all phases of digital IC development: definition, requirements mapping, architectural design, RTL, Verilog / System Verilog, synthesis, simulations, timing analysis, verification, etc.
- High level of proficiency in related aspects of digital IC design including: design flow, state machine design, CAD tool selection, synchronization, event driven simulations, STA, design-for-test (DfT), place and route (PnR), ATPG, CDC, etc.
- Experience is preferred for: design verification, clock gating / clock tree design, multiple power domains, mixed signal interface, I2C, Perl or Python, etc.
- Internal team leadership and communication, coordination of design requirements and tradeoffs, preparation for weekly meetings (internal and customer)
- Technical communication with customer (and/or marketing), including: presentation in design reviews, representing the digital design team on weekly conference calls, defining / tracking / working to insure schedule adherence, interactive problem solving and customer communication under pressure, etc
- Generation of relevant documentation
Your education and experiences
- Master’s degree in Electrical Engineering with 7 years of experience or Bachelor’s degree with 10 years of experience – with an emphasis in Digital Integrated Circuit Design or a similar specialty
- Experience and technical leadership in Digital IC Design including: RTL, simulation, modelling, timing analysis, ATPG / test insertion / scan, and verification (lint, CDC, etc.)
- Excellent communication skills (both oral and written) are required, as real time customer level technical interface and design / team leadership is necessary
- Experience with relevant CAD tools (used for digital IC design and verification)
- Excellent team player – dedicated to achieving team goals
- Experience with EM/IR: Voltus or Apache RedHawk is a plus
- Ability to perform digital design verification in a UVM environment is a plus