Principal Physical Verification Engineer

Job no.


Position Type

Research & Development

Working time

  • Regular Fulltime

Place of employment


What we offer:

Your tasks and responsibilities

  • Physical Verification for CMOS, BCD and Opto processes in analog/mixed signal, high voltage and rf applications down to 40nm
  • Integration of verification rundecks in Cadence and Mentor
  • Managing technical support for physical verification
  • Integration of verification tools in Cadence and Mentor
  • Support for the verification tools Calibre, Assura/PVS and Mentor PERC
  • Work with EDA vendors (Cadence, Mentor, etc) to report issues and find solutions to complex problems
  • Create or modify scripts (Unix shell, Tcl, Perl, Phyton) as necessary to automate common design tasks
  • Evaluate new tools for physical verification and integrate then into the ams design flow
  • Develop and deliver regular trainings to update designers with the new tool features

Your education and experiences

  • Bachelor or Master’s Degree in Electrical Engineering from an accredited college or university
  • More than 10 years of high-level technical expertise related to physical verification
  • Base know-how in semiconductor physics and processing
  • Knowledge in mask data preparation
  • Fundamental knowledge in CAD Tools, especially Mentor Cadence and Cadence Assura/PVS
  • Knowledge in IC Design
  • Excellent analytic, communication, and presentation skills

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