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Senior Design Verification Engineer

Job no.


Position Type

Research & Development

Working time

  • Regular Fulltime

Place of employment


What we offer:

Your tasks and responsibilities

  • • Responsible for planning & executing mixed-signal IC verification for 3D Systems.
  • • Write, debug, and run test-benches to verify both models and transistor-level circuits for all operating modes using the AMS-Designer environment
  • • Implement mixed-signal behavioral models in System Verilog
  • • Develop test benches with high degree of automation
  • • Generate documentation for design verification planning & execution as well as customer reviews
  • • Collaborate with digital verification engineers to achieve overall verification coverage
  • • Support IC validation and production test (ATE) development
  • • Ensure adoption of DV best practices, procedures and improvements within organization
  • • Contribute to internal and external design & verification reviews

Your education and experiences

  • • Degree in Electronic Engineering or related field
  • • Knowledge in digital and mixed-signal design and verification
  • • Good understanding of common analog blocks from schematic.
  • • Experience with Cadence AMS Designer and modelling in System Verilog
  • • Experience with Universal Verification Method (UVM) is an advantage
  • • Natural interest in EDA tools, persistent in solving software tool issues
  • • Experience in verification coverage tracking
  • • Programming skills in Linux shell, C, Perl and Tcl is an advantage
  • • Structured and methodological approach
  • • Strong team player
  • • Excellent spoken and written communication skills in English
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