Senior Staff Engineer, Digital Verification Support (m/f/d)
Research & Development
- Regular Fulltime
Place of employment
What we offer:
Your tasks and responsibilities
- Corporate Support of DV tools and DV methodology
- DV Tool management
- DV Tool Evaluation and Implementation to the ams digital Design/DV flow
- DV Tools Training and Mentoring
- DV Project Support
Your education and experiences
- Minimum 10 years’ experience in ASIC verification environment, with expertise in SystemVerilog, SVA, UVM, verification methodologies
- Experience in Simulation Tools
- Experience in Formal Verification
- Cadence vManager administration and scripting
- Team Spirit and well developed social skills are required
- Strong written and verbal communication skills
- Self-motivated and should be able to work independently
Collective salary and wage agreement
We offer competitive salaries and additional benefits based on your performance, experience and qualification.
The employment is in accordance with the collective salary and wage agreement for employees of the electrical and electronics industry, employment group H (https://www.feei.at/leistungen/informations-service/mindestlohne-und-gehalter-2019).
We offer a higher compensation depending on your expertise and skills.