jobno-004354-India

Manager, Design Verification

Job no.

004354

Position Type

Research & Development

Working time

  • Regular Fulltime

Place of employment

Hyderabad

What we offer:

Your tasks and responsibilities

  • Architect, define and drive the implementation of state of the art ASIC verification environment
  • Design and develop re-usable UVM verification methodology to identify the bugs to effectively meet our verification goals
  • Lead a team of engineers to perform digital, analog and mixed-signal verification of circuit blocks and subsystems in Cadence and Synopsys environments using UVM
  • Must be an expert in System Verilog and UVM, including: writing checkers and assertions, customizing constraints, etc. Knowledge of System C is a plus
  • Knowledge of formal verification techniques is a plus
  • Familiar with portable stimulus to effectively work with the validation team to debug issues
  • SoC/IC Verification planning: test plans, test suites and verification activities which includes environment bring-up, regressions, failure debug, and netlist simulation for tape-out, develop detailed test and coverage plans based on IC specifications
  • Advanced modeling of system modules (analog modules; functional behavior of sub-systems) in System Verilog
  • Create, debug, and run test-benches and scripts to execute transistor-level performance verification over design corners using circuit simulators
  • Develop support utilities for verification automation, test bench automation, regression and other verification enhancements to improve productivity and functional coverage
  • Establish cross-correlation matrices for Verification/Evaluation/ATE results
  • Generation of relevant documentation (DV Plan, DV execution plan, customer reviews, etc.)
  • Mentoring of staff engineers for continuous improvement of the DV flow

Your education and experiences

  • Minimum Bachelors Degree in EE, CE, Physics or related field with 10+ years experience in Mixed-Signal IC Design Verification
  • Management experience in leading a team of engineers
  • Good understanding of analog and mixed-signal CMOS IC design and experience running both analog (SPICE) and digital simulators
  • Prior mentoring experience of junior engineers would be desired
  • Experience in architecting and implementing UVM environment with strong focus on re-use
  • Experience in object oriented programming and factory methods (UVM, System Verilog and Cadence simulation tools)
  • Candidate must be able to build test bench from scratch using UVM or System Verilog
  • Demonstrated problem solving ability, analytical skills and laboratory proficiency
  • Must have excellent documentation and communication skills
  • Trained on design verification methodologies such as UVM, constraint random test generation
  • Trained on developing verification environment and test cases, conducting functional simulations, writing bug management schemes
  • Skills to understand the design specification and translate into test plan
  • Experience in writing test plan to capture all the feature of the design under test

Job Alert

 

You haven't found what you were looking for? Stay up to date and set up your personal ams job alert. Subscribe to your personal job alert now! 

Contact

 

Contact our Talent Managers