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Senior Staff Engineer, Digital Design Verification

Job no.


Position Type

Research & Development

Working time

  • Regular Fulltime

Place of employment


What we offer:

Your tasks and responsibilities

  • Implement the ASIC verification environment
  • This role requires the candidate to work with RTL Design, Verification, Architecture teams to ensure that chip meets all the feature requirements.
  • Candidate will be able to build test bench from scratch using UVM or System Verilog.
  • Develop support utilities for verification automation, test bench automation, regression and other verification enhancements to improve productivity and functional coverage.
  • Support the development of verification test plans, test suites and verification activities which includes environment bring-up, regressions, failure debug, and netlist simulation for tape-out, develop detailed test and coverage plans based on IC specifications.
  • Supporting mixed signal verification which includes analog and Verilog RTL in same simulation environment.
  • Have led a team in executing projects or should have a led a team of Verifiication engineers
  • Should have trained members in Digital verification methodologies

Your education and experiences

  • M.Tech with specialisation in Digital Design, Digital design verification using UVM, VLSI DEsign Flow, Integrated Circuits Fabrication Technology
  • Extensive experience in design verification.
  • Experienced in design verification methodologies such as UVM, assertion based coverage driven verification (code & functional coverage), constraint random test generation.
  • Experienced in developing verification environment and test cases, conducting functional simulations, writing functional cover point and meeting functional coverage goals and bug management schemes.
  • Experienced in Make and proficient in scripting using perl, shell, Tcl, etc. to automate the verification process.
  • Skills to understand the design specification and translate into test plan.
  • Experience in writing test plan to capture all the feature of the design under test and functional/Assertion coverage implementation.
  • System Verilog, UVM, object oriented programming knowledge and years of experience, Verilog.
  • Added advantage if worked in verifying mixed signal blocks in digital perspective.
  • Excellent team player, should be able to understand team dynamic.
  • Strong written and verbal communication skills.
  • Self-motivated and should be able to work independently.

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