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Senior Staff Engineer, Digital Design Verification

Job no.


Position Type

Research & Development

Working time

  • Regular Fulltime

Place of employment


What we offer:

Your tasks and responsibilities

  • Architect/define/Implement the ASIC verification environment.
  • This role requires the candidate to work proactively with RTL Design, Verification, Architecture teams to ensure that chip meets all the feature requirements. Should be able to make decision on right verification methodology based on type of design.
  • Plan, architect and develop SystemVerilog /UVM test bench, including writing checkers and assertions, customizing constraints, getting functional coverage collection using cover groups, etc. Develop test bench for ARM CPU based AMBA architecture design.
  • Develop support utilities for verification automation, test bench automation, regression and other verification enhancements to improve productivity and functional coverage.
  • Support the development of verification test plans, test suites and verification activities which includes environment bring-up, regressions, failure debug, and netlist simulation for tape-out, develop detailed test and coverage plans based on IC specifications.
  • Review the work done by juniors or verification team on every project base.
  • Supporting mixed signal verification which includes analog and Verilog RTL in same simulation environment
  • Performing block level and top level design verification
  • Technical communication with customer (and/or marketing) and other work-packages, including: presentation in design reviews, test requirements, defining / tracking / working to ensure schedule adherence, interactive problem solving and customer communication under pressure
  • Generation of relevant documentation (DV Plan, DV execution plan, customer reviews, etc.)
  • Create and patent new IPs

Your education and experiences

  • M.Tech/B.Tech in VLSI/Electronics/Electrical domain.
  • Minimum 10 years’ experience in ASIC verification environment, with expertise in systemverilog, UVM, verification methodologies
  • Experienced in design verification methodologies such as UVM, assertion based coverage driven verification (code & functional coverage), constraint random test generation.
  • Experience in defining verification environment, Test bench architecture. Must have developed test bench for CPU based design (ARM) and AMBA bus architecture.
  • Experience in generating verification plan from specification. Creating verification matrix, defining functional bins, writing functional cover point and meeting functional coverage goals and bug management schemes, with strong debugging skills. (irun, xcelium, Cadense IMC, vManager).
  • Experience in Formal Verification is plus. (JasperGold etc)
  • Strong knowledge of serial protocol like I2C, I3C, SPI etc. and its verification
  • Experienced on Make and proficient in scripting using perl, shell, Tcl, etc. to automate the verification process
  • Have led a team in executing projects or should have a led a team of verification engineers.
  • Have trained members in Digital verification methodologies
  • Added advantage if worked in verifying mixed signal blocks in digital perspective.
  • Strong knowledge of analog blocks like different ADC, DAC, Integrator, POR, Amplifiers and power management block.
  • Excellent team player, should be able to understand team dynamic.
  • Strong written and verbal communication skills.
  • Self-motivated and should be able to work independently.

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