Senior Staff Engineer, Mixed Signal Design Verification

Job no.


Position Type

Research & Development

Working time

  • Regular Fulltime

Place of employment


What we offer:

Your tasks and responsibilities

  • SoC/IC verification, lab evaluation and test concept definition as core member of project team
  • Advanced modeling of system modules (analog modules; functional behavior of sub-systems) in (System-) Verilog
  • Create, debug, and run test-benches and scripts to execute transistor-level performance verification over design corners using circuit simulators
  • Proficiency in System Verilog and UVM, including: writing checkers and assertions, customizing constraints, etc
  • Develop support utilities for verification automation, test bench automation, regression and other verification enhancements to improve productivity and functional coverage
  • Support the development of verification test plans, test suites and verification activities which includes environment bring-up, regressions, failure debug, and netlist simulation for tape-out, develop detailed test and coverage plans based on IC specifications
  • Establish cross-correlation matrices for Verification/Evaluation/ATE results
  • Generation of relevant documentation (DV Plan, DV execution plan, customer reviews, etc.)
  • Mentoring of staff engineers for continuous improvement of the DV flow

Your education and experiences

  • M.Tech/B.Tech in Electronics with at least 8 years (for M.Tech) and 10 years (for B.Tech) of experience on Mixed-Signal IC Design Verification
  • Good understanding of analog and mixed-signal CMOS IC design and experience running both analog (SPICE) and digital simulators
  • Experience in architecting and implementing UVM environment with strong focus on re-use
  • Experience in programming languages (C, Verilog A and Cadence tools)
  • Working knowledge of programming and scripting languages (C, Perl, Skill, Ocean, VerilogA/System Verilog)
  • Candidate must be able to build test bench from scratch using UVM or System Verilog
  • Demonstrated problem solving ability, analytical skills and laboratory proficiency
  • Trained on design verification methodologies such as UVM, constraint random test generation
  • Trained on developing verification environment and test cases, conducting functional simulations, writing bug management schemes

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