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Staff Engineer, Digital Design Verification
Research & Development
- Regular Fulltime
Place of employment
What we offer:
Your tasks and responsibilities
- Implement the ASIC verification environment
- This role requires the candidate to work with RTL Design, Verification, Architecture teams to ensure that chip meets all the feature requirements.
- Develop UVM / System Verilog Test bench, including writing checkers and assertions, getting functional coverage collection using cover groups, etc
- Support the development of verification test plans, test suites and verification activities which includes environment bring-up, regressions, failure debug, and netlist simulation for tape-out, develop detailed test and coverage plans based on IC specifications
- Supporting mixed signal verification which includes analog and Verilog RTL in same simulation environment.
- Develop support utilities for verification automation, test bench automation, regression and other verification enhancements to improve productivity and functional coverage
- Performing block level and top level design verification
- Generation of relevant documentation (DV Plan, DV execution plan, customer reviews, etc.)
- Create and patent new IPs
Your education and experiences
- M.Tech/B.Tech in VLSI/Electronics/Electrical domain.
- 4 -7 years’ experience in ASIC verification environment, with hands-on in systemverilog, UVM.
- Proficient in design verification methodologies such as UVM, assertion based coverage driven verification (code & functional coverage), constraint random test generation
- Experience in developing verification environment, Test bench, writing test plan to capture all the feature of the design under test and test cases, conducting functional simulations, writing functional cover point and meeting functional coverage goals, strong debugging skill and bug management schemes. (irun, xcelium, Cadense IMC, vManager)
- Strong knowledge of serial protocol like I2C, I3C, SPI etc. and its verification
- Hands-on in Make and proficient in scripting using perl, shell, Tcl, etc. to automate the verification process
- Experience in writing test plan to capture all the feature of the design under test and functional/Assertion coverage implementation.
- Experience in netlist simulation, TB adaptation for netlist and debugging.
- Experience in verifying mixed signal blocks in digital perspective is plus
- Experience in Formal Verification is plus. (JasperGold etc)
- Excellent team player, should be able to understand team dynamic, train junior.
- Strong written and verbal communication skills
- Self-motivated and should be able to work independently