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Staff Engineer, Mixed Signal Design Verification

Job no.


Position Type

Research & Development

Working time

  • Regular Fulltime

Place of employment


What we offer:

Your tasks and responsibilities

  • Analog and mixed-signal verification of circuit blocks and subsystems in Cadence and Synopsys environments using System Verilog modeling
  • Write, debug, and run test-benches using Verilog-A/Verilog-AMS/System Verilog to verify both models and transistor-level circuits for all operating modes using the AMS-Designer environment
  • Creation and validation of System Verilog models for mixed signal circuit blocks
  • Create, debug, and run test-benches and scripts to execute transistor-level performance verification over design corners using circuit simulators
  • Proficiency in System Verilog and UVM including: writing checkers and assertions, customizing constraints, etc.
  • Develop support utilities for verification automation, test bench automation, regression and other verification enhancements to improve productivity and functional coverage
  • Support the development of verification test plans, test suites and verification activities which includes environment bring-up, regressions, failure debug, and netlist simulation for tape-out, develop detailed test and coverage plans based on IC specifications
  • Performing block level and top level design verification
  • Generation of relevant documentation (DV Plan, DV execution plan, customer reviews, etc.)

Your education and experiences

  • M.Tech/B.Tech in Electronics with atleast 5 years (for M.Tech) and 7 years (for B.Tech) of experience on Mixed-Signal IC Design Verification
  • Good understanding of analog and mixed-signal CMOS IC design and experience running both analog (SPICE) and digital simulators
  • Experience in programming languages (C, Verilog A and Cadence tools)
  • Working knowledge of programming and scripting languages (C, Perl, Skill, Ocean, VerilogA/System Verilog)
  • Candidate must be able to build test bench from scratch using UVM or System Verilog
  • Demonstrated problem solving ability, analytical skills and laboratory proficiency
  • Must have excellent documentation and communication skills
  • Trained on design verification methodologies such as UVM, constraint random test generation
  • Trained on developing verification environment and test cases, conducting functional simulations, writing bug management schemes
  • Skills to understand the design specification and translate into test plan
  • Experience in writing test plan to capture all the feature of the design under test
  • Excellent presentation and communication skills
  • Initiative, enthusiasm, systematic and analytic approach
  • Team player/driver
  • Affinity with sensors and lasers
  • Fluency in English: written and verbal
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