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Principal Mixed-Signal Verification Engineer
Research & Development
- Regular Fulltime
Place of employment
What we offer:
Your tasks and responsibilities
- SoC/IC verification, lab evaluation and test concept definition as core member of project team.
- Verification planning: Define test flow and testcases to meet coverage requirements and silicon coverage.
- Advanced modeling of system modules (analog modules; functional behavior of sub-systems) in (System-) Verilog.
- Implementation of UVCs and re-use concept.
- Implementation of UVM reference model.
- SW tool implementation and improvements for verification; scripting to increase level of automation.
- Implementation and maintenance of data structures for verification specifications, test implementations, results.
- Generation of ATE test patterns for test program implementation. Support for ATE test program debug activities together with the Test Engineering department.
- Establish cross-correlation matrices for Verification/Evaluation/ATE results.
- Coverage and progress reporting.
- Co-ordination and guidance of internal and external members of project verification team.
- Take part in Design-/Test-FMEAs during the project development phase.
Your education and experiences
- Degree in the electronic engineering field
- 5+ years experience in advanced mixed-signal SoC verification with OVM/UVM, vPlan, ePlanner
- Experience in architecting and implementing UVM environment with strong focus on re-use
- Advanced skills in SystemVerilog/VerilogAMS for verification and modeling (wreal, eenet)
- Coverage metrics implementation (cover groups; assertions)
- Background in mixed-signal/RF SoC design and/or test desirable
- Knowledge of mixed-signal SoC evaluation and test methodologies and related HW
- Programming and scripting languages: Linux shell, C, Python, Tcl
- Knowledge of embedded CPU systems (ARM Cortex-M) and FW programming
- Strong team player; experience in communication between Design/Test/Evaluation teams
- Communication skills and proficiency in English