Customers developing and designing their own integrated circuit usually provide a verified design database to ams.
The design interface for foundry projects can be provided in the following formats:
- Verified design netlist with ams standard cells, referred to as semivalidated netlist (SVNL) interface in Cadence, Mentor, Synopsys, Verilog or EDIF format
- Verified layout database. Format is GDSII. The foundry input document specifies the interface requirements
Today more than 90% of the foundry projects entrusted to the company include a verified layout database interface.
An experienced and highly skilled team of engineers and project managers is responsible for the handling of all silicon foundry projects during the development phase. The same team is also responsible for the organization and execution of the ams´ multiproject wafer train service. Sales offices are updated daily on the foundry project development status.
A project engineer is assigned to each new foundry project and is in charge of the execution of the technical and administrative tasks from database input through to the manufacture of samples and or volume production. ams provides a variety of proven foundry services and a wide range of special services such as:
See a collection of all Special Engineering Services offered by ams.
If your product is anticipated to be manufactured in high volume production at ams, a design review at ams is mandatory.
For GDSII database input, ams offers a layout verification service based on our sign-off check tools from several EDA tool providers.
Verification of the test vector database with customer specified input and expected output stimuli can be offered.
Will your chip survive ESD Testing?
Integrated Circuits themselves do not produce high electromagnetic emissions but they are often found to be one of the emission sources of the electronic product in which they are integrated.